Fujitsu MB90335 Series Hardware Manual page 119

CHAPTER 3 INTERRUPT
3.8 Interruption by μDMAC
Note:
If writing transmission data to UART by using μDMAC, not setting RDY2 and RDY1 bit of DMACS
register in (0, 0).
98
Figure 3.8-10 Wait Specification Bit Explanation
source destination
Length of wait part in transfer such as above
figure is defined by RDY2 and RDY1.
FUJITSU MICROELECTRONICS LIMITED
wait source
MB90335 Series
destination
CM44-10137-6E