I 2 C Bus Data Register 0 (Idar0) - Fujitsu MB90335 Series Hardware Manual

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CHAPTER 19 I C INTERFACE
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19.2 I C Interface Register
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19.2.5 I C Bus Data Register 0 (IDAR0)
The configuration and functions of I
2
■ I
C Bus Data Register 0 (IDAR0)
Figure 19.2-9 shows the bit configuration of the I
Figure 19.2-9 Bit Configuration of I
ch.0:000074
R/W : Readable/Writable
X : Undefined value
[bit7 to bit0] D7 to D0
It is a data bit.
It is the data register used for the serial transfer, and transferred from MSB. During the data receiving
(TRX= 0), the data output value becomes "1".
The writing side of IDAR0 register is double buffering. If the bus is in use (BB=1), the data to be
written to is loaded to the register for serial transferring when each byte is transferred. In reading the
register for serial transferring is directly read, so the receiving data is valid only when INT bit is set.
446
2
C bus data register 0 (IDAR0) are described.
bit 7 6 5 4
H
D7 D6 D5 D4
R/W R/W R/W R/W
FUJITSU MICROELECTRONICS LIMITED
2
C bus data registers 0 (IDAR0).
2
C Bus Data Register 0 (IDAR0)
3 2 1 0
IDAR0
2
D3 D2 D1 D0 I C Bus data register 0
Initial value
R/W R/W R/W R/W
MB90335 Series
XXXXXXXX
B
CM44-10137-6E