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CHAPTER 9 TIME-BASE TIMER
9.4 Interrupt of Time-base Timer
9.4
Interrupt of Time-base Timer
The time-base timer can generate an interrupt request by the overflow of the specified
bit of the time-base timer counter (interval timer function).
■ Interrupt of Time-base Timer
After the time-base counter undergoes count-up with the internal count clock and the bit for the selected
interval timer overflows, the interrupt request flag bit (TBOF) of time-base timer control register (TBTC) is
set to "1". In this case, an interrupt request to CPU is generated if interrupt request is permitted by setting
the interrupt request permission bit (TBIE) is set to "1". Clear the interrupt request by writing "0" to the
TBOF bit in the interrupt processing routine. The TBOF bit is set when the specified bit overflows
regardless of the value of interrupt request permission bit (TBIE).
Note:
When clearing the interrupt request flag bit (TBOF) in the time-base timer control register (TBTC),
perform while the time-base timer interrupt is prohibited by the setting of the interrupt level mask
register (ILM) of the interrupt request permission bit (TBIE) or the processor status (PS).
References:
•
When the TBOF bit is "1", an interrupt request is immediately generated upon the transition of the
TBIE bit from prohibition to permission ("0" → "1").
2
OS and μDMAC cannot be used.
•
EI
■ Interrupt of Time-base Timer and EI
Table 9.4-1 shows the time-base timer interrupt and EI
Table 9.4-1 Interrupt of Time-base Timer and EI
Interrupt level setting register
Interrupt
number
Register Name
#40
ICR14
: Not available
Note:
ICR14 can be used for three interrupts, time-base timer interrupt, watch timer interrupt, and UART
reception end ch.0/ch.1 interrupt, but the interrupt level is the same.
176
2
OS, μDMAC
2
OS, μDMAC
Address in Vector Table
Address
Low
0000BE
FFFF5C
H
FUJITSU MICROELECTRONICS LIMITED
2
OS, μDMAC.
High
Bank
FFFF5D
FFFF5E
H
H
MB90335 Series
μDMAC
2
EI
OS
H
CM44-10137-6E
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