Table of Contents
Advertisement
MB90335 Series
■ Interrupt Control Register Functions
●
Interrupt level set bits (IL2 to IL0)
Specifies the interrupt level for the associated peripheral function. Initialized to level 7 (no interrupts) by
reset. Table 3.3-2 shows the relationship between the interrupt level set bits and each interrupt level.
Table 3.3-2 Correspondence between Interrupt Level Set Bits and Interrupt Levels
●
2
EI
OS enable bit (ISE)
If the ISE bit is "1" during generation of an interrupt request, EI
sequence will be activated. Furthermore, when the end condition of EI
bits are other than "00
2
EI
OS function, the ISE bit must have been set to "0" by software. The ISE bit is initialized to "0" by reset
by "0000
●
2
EI
OS channel select bits (ICS3 to ICS0)
Specifies the channel of EI
the value set here. The ICS bit is initialized to "0000
between the EI
CM44-10137-6E
IL2
0
0
0
0
1
1
1
1
"), the ISE bit is cleared. If the associated peripheral function does not have the
B
".
B
2
OS with a write only bit. The address of the EI
2
OS channel select bits and descriptor addresses.
FUJITSU MICROELECTRONICS LIMITED
3.3 Interrupt Control Register and Peripheral Function
IL1
0
0
1
1
0
0
1
1
" by reset by. Table 3.3-3 shows the correspondence
B
CHAPTER 3 INTERRUPT
IL0
Interrupt level
0
0 (highest interrupt)
1
0
1
0
1
0
6 (lowest interrupt)
1
7 (No interrupt)
2
OS is activated; if it is "0", the interrupt
2
OS is satisfied, (both the S1 and S0
2
OS descriptor is determined by
57
Advertisement
Table of Contents
