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MB90335 Series
3.8.2.4
DMA Enable Register (DERH/DERL)
DMA enable register (DERH/DERL) enables the DMA transfer.
When "1" is set to this register, the interrupt request, which is the DMA transfer
request, generates to the corresponding channel, and starts the DMA transfer.
■ DMA Enable Register (DERH/DERL)
Figure 3.8-5 Bit Configuration of DMA Enable Register (DERH/DERL)
bit
0000AD
EN15
H
R/W
bit
0000AC
EN7
H
R/W
R/W: Readable/Writable
[bit15 to bit0] ENx: DMA permission
ENx bit
0 [Initial value]
This bit does not execute the DMA transfer.
The interrupt request from the resource is handled as a DMA activation request, and the interrupt
request is output to the interrupt controller at the end of DMA transfer.
1
When the number of DMA transfer bytes reaches 0, or a STOP request from the resource stops DMA
transfer, this is cleared to "0".
Notes:
•
To write data to the DERH/DERL, use a read modify write (RMW) instruction.
•
Before changing the mode to the standby mode (sleep mode, stop mode, watch mode, and time-
base timer mode) or the CPU intermittent operation mode (main clock intermittent operation
mode and PLL clock intermittent mode), the DMA enable register must be set to "0".
CM44-10137-6E
15
14
13
EN14
EN12
EN13
R/W
R/W
R/W
7
6
5
EN5
EN6
R/W
R/W
R/W
FUJITSU MICROELECTRONICS LIMITED
12
11
10
EN11
EN10
R/W
R/W
4
3
2
EN4
EN3
EN2
R/W
R/W
Function
CHAPTER 3 INTERRUPT
3.8 Interruption by μDMAC
9
8
DERH
EN8
EN9
R/W
R/W
Initial value
1
0
EN1
DERL
EN0
R/W
R/W
Initial value
00000000
B
00000000
B
93
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