Fujitsu MB90335 Series Hardware Manual page 622

DIVR
PWC Ratio of Dividing Frequency Control Register (DIVR)
.......................................................... 299
DMA Buffer Address Pointer
DMA Buffer Address Pointer (DBAPH/DBAPM/DBAPL)
............................................................ 99
DMA Control Register
DMA Control Register (DMACS)
DMA Data Counter
About the Set Value of DMA Data Counter
(DDCTH/DDCTL)
DMA Data Counter (DDCTH/DDCTL)
DMA Descriptor
Each Register of DMA Descriptor
DMA Descriptor Channel Specification Register
DMA Descriptor Channel Specification Register (DCSR)
............................................................ 88
DMA Descriptor Window Register
Configuration of DMA Descriptor Window Register
................................................ 94
(DDWR)
DMA Enable Register
DMA Enable Register (DERH/DERL)
DMA I/O Register Address Pointer
DMA I/O Register Address Pointer (DIOAH/DIOAL)
............................................................ 96
DMA Status Register
Bit Configuration of DMA Status Register (DSRH/DSRL)
............................................................ 90
DMA Stop Status Register
DMA Stop Status Register (DSSR)
DMACS
DMA Control Register (DMACS)
DPR
Direct Page Register (DPR)<Initial Value: 01
DQ3
Sector Erase Timer Flag (DQ3)
DQ5
Timing Limit Over Flag (DQ5)
DQ6
......................................... 498
Toggle Bit Flag (DQ6)
DQ7
Data Polling Flag (DQ7)
DSRH
Bit Configuration of DMA Status Register (DSRH/DSRL)
............................................................ 90
DSRL
Bit Configuration of DMA Status Register (DSRH/DSRL)
............................................................ 90
DSSR
DMA Stop Status Register (DSSR)
DTB
Bank Registers (PCB, DTB, USB, SSB, ADB)
DTP
............................................... 362
Operation of DTP
DTP/External Interrupt
Block Diagram of DTP/External Interrupt
............................ 97
................................... 95
..................... 95
............................ 94
...................... 93
........................... 91
............................ 97
.......... 38
>
H
.............................. 500
.............................. 499
...................................... 496
........................... 91
............ 37
................ 358
Operation Process of DTP/External Interrupt
Overview of DTP/External Interrupt
Register List of DTP/External Interrupt
DTP/Interruption Factor register
DTP/Interruption Factor Register (EIRR: External Interrupt
Request Register)
DTP/Interruption Permission Register
DTP/Interruption Permission Register (ENIR: Enable
Interrupt Request Register)
Dual Operation Flash Memory
Features of Dual Operation Flash Memory
Overview of Dual Operation Flash Memory
Sector and Bank Configuration of Dual Operation Flash
...............................................478
Memory
E
2
E
PROM
2
........................................469
E PROM Memory Map
Operation of Address Match Detection Function at Storing
Patch Program in E
System Configuration and E
..........................................................468
Each Register Operation
Each Register Operation when Read Command Responds
..........................................................229
Each Register Operation when Write Command Responds
..........................................................230
Effective Address Field
................................539, 557
Effective Address Field
2
EI
OS
Configuration of Extended Intelligent I/O Service (EI
Descriptor (ISD)
Extended Intelligent I/O Service (EI
Extended Intelligent I/O Service (EI
(Time for One Transfer)
Extended Intelligent I/O Service (EI
...................................................77
(ISCS)
Interrupt of Time-base Timer and EI
..........................................................176
Interruption of UART, EI
Operation of Extended Intelligent I/O Service (EI
......................................................73, 79
Procedure for Use of Extended Intelligent I/O Service
2
..................................................80
(EI OS)
2
.........................................405
UART EI OS Function
EIRR
DTP/Interruption Factor Register (EIRR: External Interrupt
Request Register)
ELVR
Request Level Setting Register (ELVR: External Level
..............................................360
Register)
End Timing
..............................................282
Packet End Timing
ENIR
DTP/Interruption Permission Register (ENIR: Enable
Interrupt Request Register)
EOF Setting Register
EOF Setting Register (HEOF)
.............364
........................358
....................359
...................................360
.......................359
................476
..............476
2
......................471
PROM
2
PROM Memory Map
2
OS)
......................................74
2
....................72
OS)
2
OS) Processing Time
.............................81
2
OS) Status Register
2 OS, μDMAC
2 OS, and μDMAC
..............405
2
OS)
...................................360
.......................359
................................266
601