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CHAPTER 21 ADDRESS MATCH DETECTION FUNCTION
21.4 Explanation of Operation of Address Match Detection Function
■ Flow of Patch Processing
Figure 21.4-5 shows the flow of patch processing using the address match detection function.
000000
H
000100
H
000400
H
000480
H
000900
H
FF0000
H
FF8000
H
FF8050
H
FFFFFF
H
472
Figure 21.4-5 Flow of Patch Processing
MB90335 series
I/O area
Register/RAM area
Patch program
RAM area
Stack area
Detection address setting register
Program error
Reset
Read the 00
H
2
of E
PROM
YES
2
E
PROM : 0000
H
= 0
NO
Read detect address
2
E
PROM : 0001
to 0003
H
↓
MCU : Set to PADR0
Read patch program
2
E
PROM : 0010
to 008F
H
↓
MCU : 000400
to 00047F
H
Enable address match detection
(PACSR : AD0E = 1)
Execution of normal
program
NO
Program address
PC= PADR0
FUJITSU MICROELECTRONICS LIMITED
0000
0001
0002
0003
RAM
0010
0090
FFFF
ROM
Branch to patch program
Execution of patch program
End of patch program
H
H
H
YES
INT9
MB90335 Series
2
E
PROM
Patch program byte count : 80
H
Detect address (Low) : 00
H
Detect address (Middle) : 80
H
Detect address (High) : FF
H
Patch program
H
H
H
INT9
JMP 000400H
000400
to 000480
H
H
JMP FF8050H
H
H
H
H
CM44-10137-6E
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