Packet End - Fujitsu MB90335 Series Hardware Manual

CHAPTER 12 USB HOST
12.5 Operation of USB HOST
12.5.9

Packet End

When one packet terminates in USB HOST, if the CMPIRE bit of the host control register
0 (HCNT0) is "1", an interrupt is generated to set the CMPIRQ bit of the host interrupt
register (HIRQ) to "1".
■ Packet End Timing
When one packet terminates, an interrupt is generated in the following timing:
When the TKNEN bits of the host token end point register (HTOKEN) are 001
token, IN token, and OUT token)
Figure 12.5-9 CMPIRQ Bit Set Timing Example 1 of HOST Interrupt Register (HIRQ)
To the TKNEN bit of HTOKEN
Write
J-ST
CMPIRQ bit
(HIRQ)
When the TKNEN bit of the host token end point register (HTOKEN) is 100
Figure 12.5-10 CMPIRQ Bit Set Timing Example 2 of HOST Interrupt Register (HIRQ) (SOF TOKEN)
CMPIRQ bit
(HIRQ)
282
Token packet
Sync TKN ADR ENDPT CRC5 EOP J-ST
To the TKNEN bit of HTOKEN
Write
J-ST Sync TKN FRAME
FUJITSU MICROELECTRONICS LIMITED
data packet
Sync DATA CRC16 EOP
TGGL
J-ST
TKN
ADR
ENDPT
TGGL
CRC5 EOP J-ST
J-ST
TKN
FRAME
MB90335 Series
, 010 or 011
B B
handshake packet
J-ST Sync ACK EOP J-ST
: J State
: Token
: Address
: Endpoint
: Toggle
(SOF token)
B
:J State
:Token
:Frame Number
CM44-10137-6E
(SETUP
B