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LVM—Level Mask 0–7
When set, these bits enable a LEVELx interrupt request from an internal source to be
generated. The SIPEND register contains the corresponding LVLx bits. See Figure 12-2 for
more information.
0 = Disable the generation of an IRQx bit in the SIPEND register.
1= Enable the generation of an IRQx bit in the SIPEND register.
Bits 16–31—Reserved
These bits are reserved and must be set to 0.
12.3.3.3 SIU INTERRUPT EDGE/LEVEL REGISTER. The 32-bit read/write SIU interrupt
edge/level (SIEL) register contains pairs of bits that correspond to an external interrupt
request. If set, the EDx bit specifies when a falling edge in the corresponding IRQx signal is
an interrupt request. When the EDx bit is 0, a low logical level in the IRQx signal is an
interrupt request. The WMx bit, if set, indicates that a low level detection in the
corresponding interrupt request line causes the MPC823e to exit low-power mode.
SIEL
BIT
0
1
2
FIELD
ED0 WM0 ED1 WM1 ED2 WM2 ED3 WM3 ED4 WM4 ED5 WM5 ED6 WM6 ED7 WM7
RESET
0
0
0
R/W
R/W
R/W
R/W
ADDR
BIT
16
17
18
FIELD
RESET
R/W
ADDR
ED—Edge Detect 0–7
0 = The bits specify that a low logical level in the IRQx signal is detected as an interrupt
request.
1 = The bits specify that a falling edge in the corresponding IRQx signal is detected as
an interrupt request.
WM—Wake-Up Mask 0–7
0 = Not allowed to exit from low-power mode.
1 = Allows low-level detection in the corresponding IRQx signal to exit or wake up the
MPC823e from low-power mode.
MOTOROLA
3
4
5
6
7
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
(IMMR & 0xFFFF0000) + 0x018
19
20
21
22
23
RESERVED
0
R/W
(IMMR & 0xFFFF0000) + 0x018
MPC823e REFERENCE MANUAL
System Interface Unit
8
9
10
11
12
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
24
25
26
27
28
13
14
15
0
0
0
R/W
R/W
R/W
29
30
31
12-9
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