Implementation-Specific Instruction Tlb Error; Implementation-Specific Data Tlb Error - Motorola MPC823e Reference Manual

Memory Management Unit

11.7.3 Implementation-Specific Instruction TLB Error

The implementation-specific instruction TLB error interrupt occurs under one of the following
conditions:
• The effective address cannot be translated. Either the segment or page valid bit of this
page is cleared in the translation table.
• The fetch access violates storage protection.
• The fetch access is to guarded storage and MSR
The cause of an instruction TLB error interrupt can be found in the save/restore register 1
(SRR1). For bit assignments, refer to Section 7.3.7.3.12 Implementation-Specific
Instruction TLB Error Interrupt. It is the software's responsibility to invoke the instruction
storage interrupt handler.

11.7.4 Implementation-Specific Data TLB Error

The implementation-specific data TLB error interrupt occurs under one of the following
conditions:
• The effective address of a load, store, icbi, dcbz, dcbst, dcbf, or dcbi instruction
cannot be translated. Either the segment or page valid bit of this page is cleared in the
translation table.
• The access violates storage protection.
• An attempt is made to write to a page with a negated change bit.
The data storage interrupt status register indicates the cause of the data TLB error interrupt.
For bit assignments refer to Section 7.3.7.3.14 Implementation-Specific Data TLB Error
Interrupt. It is the software's responsibility to invoke the data storage interrupt handler.
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