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Memory Management Unit
SFP—Privileged (Supervisor) Fetch Permission
Bit 28:
0 = Subpage 0 (address[20:21]=00) privileged fetch is not permitted.
1 = Subpage 0 (address[20:21]=00) privileged fetch is permitted.
Bit 29:
0 = Subpage 1 (address[20:21]=01) privileged fetch is not permitted.
1 = Subpage 1 (address[20:21]=01) privileged fetch is permitted.
Bit 30:
0 = Subpage 2 (address[20:21]=10) privileged fetch is not permitted.
1 = Subpage 2 (address[20:21]=10) privileged fetch is permitted.
Bit 31:
0 = Subpage 3 (address[20:21]=11) privileged fetch is not permitted.
1 = Subpage 3 (address[20:21]=11) privileged fetch is permitted.
11.6.3.3 MMU INSTRUCTION RAM ENTRY READ REGISTER 1. The MMU instruction
RAM entry read register 1 (MI_RAM1) contains the protection mode information of the entry
indexed by the ITLB_INDX field of the MI_CTR. This register is only updated when you write
to the MI_CAM register.
MI_RAM1
BIT
0
1
2
FIELD
RESET
R/W
ADDR
BIT
16
17
18
FIELD
RESET
R/W
ADDR
NOTE: — = Undefined.
Bits 0–25—Reserved
These bits are reserved and must be set to zero.
11-46
3
4
5
6
7
RESERVED
0
R
SPR 818
19
20
21
22
23
RESERVED
0
R
SPR 818
MPC823e REFERENCE MANUAL
8
9
10
11
12
24
25
26
27
28
UFP
—
R
13
14
15
29
30
31
PV
G
—
—
R
R
MOTOROLA
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