Erase Block Register 2 (Ebr2) - Renesas H8 Series Hardware Manual

Section 6 ROM
6.5.3

Erase Block Register 2 (EBR2)

EBR2 is an 8-bit register that specifies small flash-memory blocks for programming or erasure.
EBR2 is initialized to H'00 upon reset, in sleep mode, subsleep mode, watch mode, and standby
mode, and when 12 V is not applied to FV
block is selected and can be programmed and erased. The erase block map is shown in figure 6.7,
and the correspondence between bits and erase blocks is shown in table 6.8.
Bit
SB7
Initial value
R/W *
Read/Write
Note: * Word access cannot be used on this register; byte access must be used. For
information on access to this register, see note 11 in section 6.9, Flash Memory
Programming and Erasing Precautions. LB3 is invalid in the H8/3643F, and LB3 and
LB2 are invalid in the H8/3642AF.
Bits 7 to 0    Small Block 7 to 0 (SB7 to SB0): These bits select small blocks (SB7 to SB0) to be
programmed and erased.
Bits 7 to 0:
SB7 to SB0 Description
0 Block SB7 to SB0 is not selected
1 Block SB7 to SB0 is selected
Rev. 6.00 Sep 12, 2006 page 118 of 526
REJ09B0326-0600
PP
7 6 5
SB6 SB5
0 0 0
R/W * R/W *
. When a bit in EBR2 is set to 1, the corresponding
4 3
SB4 SB3
0 0
R/W * R/W *
2 1
SB2 SB1 SB0
0 0
R/W * R/W * R/W *
(initial value)
0
0