Erase Flowcharts And Sample Programs - Renesas H8 Series Hardware Manual

6.7.6

Erase Flowcharts and Sample Programs

Flowchart for Erasing One Block
Set erase block register
(set bit for block to be erased to 1)
Write 0 data in all addresses to be erased
Enable watchdog timer
(E bit = 1 in FLMCR)
Disable watchdog timer
Set block start address as
Select erase-verify mode
Dummy write to verify address
(flash memory latches
No
Address + 1 → address
Clear erase block register
(clear bit for erased block to 0)
Start
*1
(prewrite)
n = 1
*2
Select erase mode
*5
Wait (x) ms
Clear E bit Erasing halts
verify address
(EV bit = 1)
*6
Wait (t ) µs
vs1
*3
address)
*6
Wait (t ) µs
vs2
*4
Verify
NG
(read data H'FF?)
OK
Last address?
Yes
Clear EV bit
End of erase
Figure 6.14 Erase Flowchart
Notes: 1. Program all addresses to be erased by
following the prewrite flowchart.
2. Set the watchdog timer overflow interval to
the initial value shown in table 6.12.
3. For the erase-verify dummy write, write H'FF
using a byte transfer instruction.
4. For the erase-verify operation, read the data
using a byte transfer instruction. When
erasing multiple blocks, clear the erase block
register bits for erased blocks and perform
additional erasing only for unerased blocks.
5. Erase time x is successively incremented to
initial set value x 2n-1 (n = 1 to 4), and is
fixed from the 4th time onward. An initial
value of 6.25 ms or less should be set, and
the time for one erasure should be 50 ms or
less.
6. t : 4 µs or more
vs1
t : 2 µs or more
vs2
N: 602 (set N so that the total erase time
does not exceed 30 s)
End of erase-verify
Clear EV bit
No
n ≥ N?
*6
Yes
Erase error
Double the erase time
Rev. 6.00 Sep 12, 2006 page 133 of 526
Section 6 ROM
n + 1 → n
Yes
n > 4?
No
(x × 2 → x)
REJ09B0326-0600