Register Descriptions - Renesas H8 Series Hardware Manual

Section 9 Timers
9.5.2

Register Descriptions

Free-Running Counter (FRC)
Free-Running Counter H (FRCH)
Free-Running Counter L (FRCL)
Bit
15
Initial value
0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
FRC is a 16-bit read/write up-counter, which is incremented by internal or external clock input.
The clock source is selected by bits CKS1 and CKS0 in TCRX.
FRC can be cleared by compare match A, depending on the setting of CCLRA in TCSRX.
When FRC overflows from H'FFFF to H'0000, OVF is set to 1 in TCSRX. If OVIE = 1 in TIER, a
CPU interrupt is requested.
FRC can be written and read by the CPU. Since FRC has 16 bits, data is transferred between the
CPU and FRC via a temporary register (TEMP). For details see section 9.5.3, CPU Interface.
FRC is initialized to H'0000 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
Output Compare Registers A and B (OCRA, OCRB)
Output Compare Registers AH and BH (OCRAH, OCRBH)
Output Compare Registers AL and BL (OCRAL, OCRBL)
Bit
15
Initial value
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 6.00 Sep 12, 2006 page 242 of 526
REJ09B0326-0600
14 13 12 11 10
0 0 0 0
FRCH
14 13 12 11 10
1 1 1 1
OCRAH, OCRBH
FRC
9 8 7 6
0 0 0 0 0
OCRA, OCRB
9 8 7 6
1 1 1 1 1
5 4 3 2 1
0 0 0 0 0
FRCL
5 4 3 2 1
1 1 1 1 1
OCRAL, OCRBL
0
0
0
1