Timer Operation - Renesas H8 Series Hardware Manual

Section 9 Timers
9.6.3

Timer Operation

The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input (φ/8192).
When TCSRWE = 1 in TCSRW, if 0 is written in B2WI and 1 is simultaneously written in
WDON, TCW starts counting up (two write accesses to TCSRW are necessary in order to operate
the watchdog timer). When the TCW count value reaches H'FF, the next clock input causes the
watchdog timer to overflow and generates an internal reset signal. The internal reset signal is
output for 512 clock cycles of the φ
count up from the written value. The overflow period can be set in the range from 1 to 256 input
clocks, depending on the value written in TCW.
Figure 9.36 shows an example of watchdog timer operations.
Example: φ = 4 MHz and the desired overflow period is 30 ms.
4 × 10
6
8192
The value set in TCW should therefore be 256 – 15 = 241 (H'F1).
H'FF
H'F1
TCW count
value
H'00
H'F1 written
in TCW
Internal reset
signal
Figure 9.36 Typical Watchdog Timer Operations (Example)
Rev. 6.00 Sep 12, 2006 page 274 of 526
REJ09B0326-0600
clock. It is possible to write to TCW, causing TCW to
OSC
× 30 × 10
–3
= 14.6
Start
H'F1 written in TCW
TCW overflow
Reset
512 φ
clock cycles
OSC