Motorola CPU32 Reference Manual page 335

II
Note that many instructions listed as having negative tails are change of flow
instructions, and that the bus speed used in the calculation is that of the new
instruction stream.
8.2 Instruction Stream Timing Examples
The following programming examples provide a detailed examination of timing
effects. In all examples, memory access is either from internal two-clock
memory or from external synchronous memory, the bus is idle, and the
instruction pipeline is full at start.
8.2.1 Timing Example 1: Execution Overlap
Figure 8-4 illustrates execution overlap caused by the bus controller's
completion of bus cycles while the sequencer is calculating the next effective
address. One clock is saved between instructions, as that is the minimum time
of the individual head and tail numbers.
CLOCK
BUS
CONTROLLER
INSTRUCTION
CONTROLLER
2 4
Instructions
MOVE.W
ADDQ.W
CLR.W
A1, (AO)
+
#1, (AO)
$30 (A1)
~--~~~~rm
MOVEA1,(AO)+
4
3 PRE- WRITE
FETCH FOR3
CLR
<EA>
r---~~~
..
~~~~~~
EXECUTION MOVE.W A1,(AO)+ CLR.W $30(A1)
TIME
L ______
.J] _ _ _ _ _ _ _ _ _ _
L _______
~
MOTOROLA
8-8
Figure 8-4. Example 1 - Instruction Stream
INSTRUCTION EXECUTION CPU32 REFERENCE MANUAL
TIMING