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Figure 7-7 represents the timing required for asserting BKPT during a single
bus cycle.
FORCE_BGND - - - - - - - - - - - - - - - - - - - - - - - - -
~~-------------------
FREEZE _ _ _ _ ----'
L
Figure 7-7. BKPT Timing for Single Bus Cycle
Figure 7-8 depicts the timing of the BKPT/FREEZE method. In both cases, the
serial clock is left high after the final shift of each transfer. This technique
eliminates the possibility of accidentally tagging the prefetch initiated at the
conclusion of a BDM session. As mentioned previously, all timing within the
CPU is derived from the rising edge of the clock; the falling edge is effectively
ignored.
FORCE_BGND
----.J
LLI
1 ..... 11 ...... 1 1 ...... 1Iu.1 ..... 1 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
FREEZE _ _ _ _ ----'
L
Figure 7-8. BKPT Timing for Forcing BOM
Figure 7-9 represents a sample circuit providing for both BKPT assertion
methods. As the name implies, FORCE_BGND is used to force a transition into
BDM by the assertion of BKPT. FORCE_BGND can be a short pulse or can
remain asserted until FREEZE is asserted. Once asserted, the set-reset latch
holds BKPT low until the first SHIFT _ClK is applied.
CPU32 REFERENCE MANUAL
DEVELOPMENT SUPPORT
MOTOROLA
7-13
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