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8.1.3 Bus Controller Resources
The bus controller consists of the instruction prefetch controller, the write-
pending buffer, and the microbus controller. These three resources transact all
reads, writes, and instruction prefetches required for instruction execution.
The bus controller and microsequencer operate concurrently.
The bus
controller can perform a read or write, or schedule a prefetch, while the
microsequencer controls effective address calculation or sets condition codes.
The microsequencer can also request a bus cycle that the bus controller cannot
perform immediately. When this happens, the bus cycle is queued, and the bus
controller runs the cycle when the current cycle is complete.
8.1.3.1 Prefetch Controller
The instruction prefetch controller receives an initial request from the
microsequencer to initiate prefetching at a given address.
Subsequent
prefetches are initiated by the prefetch controller whenever a pipeline stage is
invalidated, either through instruction completion or through use of extension
words.
Prefetch occurs as soon as the bus is free of operand accesses
previously requested by the microsequencer.
Additional state information
permits the controller to inhibit prefetch requests when a change in instruction
flow (e.g. a jump or branch instruction) is anticipated.
In a typical program, 10 to 25 percent of the instructions causes a change of
flow. Each time a change occurs, the instruction pipeline must be flushed and
refilled from the new instruction stream. If instruction prefetches, rather than
operand accesses, were given priority, many instruction words would be
flushed unused, and necessary operand cycles would be delayed.
To
maximize available bus bandwidth, the CPU32 will schedule a prefetch only
when the next instruction is not a change-of-flow instruction, and when there is
room in the pipeline for the prefetch.
8.1.3.2 Write-pending Buffer
The CPU32 incorporates a single-operand write-pending buffer. The buffer
permits the microsequencer to continue execution after a request for a write
cycle is queued in the bus controller. The time needed for a write at the end of
_
-.
an instruction can overlap the head cycle time for the following instruction, and
thus reduce overall execution time. Interlocks prevent the microsequencer from
overwriting the buffer.
CPU32 REFERENCE MANUAL
INSTRUCTION EXECUTION
TIMING
MOTOROLA
8-3
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