Motorola CPU32 Reference Manual page 103

M68300 series central processor unit
Hide thumbs Also See for CPU32:
Table of Contents

Advertisement

BSET
Test a Bit and Set
BSET
Instruction Fields (Bit Number Static):
Bit Number field -
Specifies the bit number.
Effective Address field - Specifies the destination location. Only data alterable addressing
modes are allowed as shown:
Addressing Mode
Mode
Register
Addressing Mode Mode
Register
Dn*
000
Reg. number: Dn
(xxx).w
111
000
An
-
-
(xxx).L
111
001
(An)
010
Reg. number: An
#(data)
-
-
(An)
+
011
Reg. number: An
-(An)
100
Reg. number: An
(d16, An)
101
Reg. number: An
(d16, PC)
-
-
(da, An, Xn)
110
Reg. number: An
(da, PC, Xn)
-
-
(bd, An, Xn)
110
Reg. number: An
(bd, PC, Xn)
-
-
*Long only; all others are byte only
Instruction Format (Bit Number Dynamic, specified In a register):
15
14
13
12
11
10
9
a
7
6
5
4
3
2
EFFECTIVE ADDRESS
0
0
0
0
REGISTER
1
1
1
I
MODE
REGISTER
Instruction Fields (Bit Number Dynamic):
Register field -
Specifies the data register that contains the bit number.
Effective Address field - Specifies the destination location. Only data alterable addressing
modes are allowed as shown:
Addressing Mode
Mode
Register
Addressing Mode Mode
Register
Dn*
000
Reg. number: Dn
(xxx).w
111
000
An
-
-
(xxx).L
111
001
(An)
010
Reg. number: An
#(data)
-
-
(An) +
011
Reg. number: An
-(An)
100
Reg. number: An
(d16, An)
101
Reg. number: An
(d16, PC)
-
-
(d8, An, Xn)
110
Reg. number: An
(da, PC, Xn)
-
-
(bd, An, Xn)
110
Reg. number: An
(bd, PC,Xn)
-
-
*Long only; all others are byte only
o
MOTOROLA
4-50
INSTRUCTION SET
CPU32 REFERENCE MANUAL

Advertisement

Table of Contents
loading

Table of Contents