Motorola CPU32 Reference Manual page 297

80M can be initiated in several ways - by externally generated breakpoints, by
internal peripheral breakpoints, by the background (8GNO) instruction, or by
catastrophic exception conditions. While in 80M, the CPU32 ceases to fetch
instructions via the parallel bus and communicates with the development
system via a dedicated, high-speed, SPI-type serial command interface.
7.2.1 Enabling 80M
Accidentally entering 80M in a nondevelopment environment could lock up the
CPU32 since the serial command interface would probably not be available.
For this reason, 80M is enabled during reset via the breakpoint (BKPT) signal.
80M operation is enabled when BKPT is asserted (low), at the rising edge of
RESET. 80M remains enabled until the next system reset. A high BKPT signal
on the trailing edge of RESET disables 80M. BKPT is relatched on each rising
transition of RESET. BKPT is synchronized internally, and must be held low for
at least two clock cycles prior to negation of RESET
80M enable logic must be designed with special care. If hold time on BKPT
(after the trailing edge of RESET) extends into the first bus cycle following reset,
the bus cycle could inadvertently be tagged with a breakpoint. Refer to the
system integration module user's manual for timing information.
7.2.2 80M Sources
When 80M is enabled, any of several sources can cause the transition from
normal mode to 80M. These sources include external breakpoint hardware,
the 8GNO instruction, a double bus fault, and internal peripheral breakpoints. If
80M is not enabled when an exception condition occurs, the exception is
processed normally. Table 7-1 summarizes the processing of each source for
both enabled and disabled cases. As shown in Table 7-1, the BKPT instruction
never causes a transition into 80M.
MOTOROLA
7-4
Table 7-1. 80M Source Summary
Source 80M Enabled 80M Disabled
BKPT
Background
Breakpoint Exception
Double Bus Fault Background Halted
BGND Instruction
Background Illegal Instruction
BKPT Instruction
Opcode Substitution/ Opcode Substitution!
Illegal Instruction Illegal Instruction
DEVELOPMENT SUPPORT CPU32 REFERENCE MANUAL