Motorola CPU32 Reference Manual page 125

III
DIVS
DIVSL
Condition Codes:
x
N
X Not affected.
z
v
Signed Divide
C
o
DIVS
DIVSL
N Set if quotient is negative. Cleared otherwise. Undefined if overflow or divide by zero occurs.
Z Set if quotient is zero. Cleared otherwise. Undefined if overflow or divide by zero occurs.
V Set if division overflow occurs; undefined if divide by zero occurs. Cleared otherwise.
C Always cleared.
Instruction Format (word form):
15 14 13 12 11
10
9
s
7 6 5 4 3 2
a
EFFECTIVE ADDRESS
1
0
a
a
REGISTER
1 1 1
I
MODE REGISTER
Instruction Fields:
Register field - Specifies any of the eight data registers. This field always specifies the
destination operand.
Effective Address field - Specifies the source operand. Only data addressing modes are
allowed as shown:
Addressing Mode Mode Register
Addressing Mode Mode
Register
Dn
000
Reg. number: Dn (xxx).W
111 000
An
-
-
(xxx).L
111 001
(An)
010
Reg. number: An
#(data) 111 100
(An)
+ 011
Reg. number: An
-(An)
100
Reg. number: An
(d16, An) 101
Reg. number: An
(d16, PC) 111 010
(dS, An, Xn) 110
Reg. number: An
(dg, PC, Xn) 111 011
(bd, An, Xn)
110
Reg. number: An (bd, PC, Xn)
111 011
NOTE
Overflow occurs if the quotient is larger than a 16-bit signed integer.
MOTOROLA
4-72
INSTRUCTION SET CPU32 REFERENCE MANUAL