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DIVU
DIVUL
Instruction Format (word form):
15
14
13
12
11
10
Unsigned Divide
9
8
7
6
5
4
3
DIVU
DIVUL
2
o
EFFECTIVE ADDRESS
1
0
0
0
REGISTER
0
1
1
I
MODE
REGISTER
Instruction Fields:
Register field -
Specifies any of the eight data registers. This field always specifies the
destination operand.
Effective Address field -
Specifies the source operand. Only data addressing modes are
allowed as shown:
Addressing Mode
Mode
Register
Addressing Mode Mode
On
000
Reg. number: On
(xxx).w
111
An
-
-
(xxx).L
111
(An)
010
Reg. number: An
#(data)
111
(An)
+
011
Reg. number: An
-(An)
100
Reg. number: An
(d16. An)
101
Reg. number: An
(d16. PC)
111
(de. An, Xn)
110
Reg. number: An
(de. PC, Xn)
111
(bd, An, Xn)
110
Reg. number: An
(bd, PC, Xn)
111
NOTE
Overflow occurs if the quotient is larger than a 16-bit signed integer.
CPU32 REFERENCE MANUAL
INSTRUCTION SET
Register
000
001
100
010
011
011
MOTOROLA
4-75
III
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