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6.2.3 Address Error
Address error exceptions occur when the processor attempts to access an
instruction, word operand, or long-word operand at an odd address. The effect
is much the same as an internally generated bus error.
The exception
processing sequence is the same as that for bus error, except that the vector
number refers to the address error exception vector.
Address error exception processing begins when the processor attempts to use
information from the aborted bus cycle.
If the aborted cycle is a data space access, exception processing begins when
the processor attempts to use the data, except in the case of a released
operand write. Released write exceptions are delayed until the next instruction
boundary or attempted operand access.
An address exception on a branch to an odd address is delayed until the
program counter is changed. No exception occurs if the branch is not taken. In
this case, the fault address and return program counter value placed in the
exception stack frame are the odd address, and the current instruction program
counter points to the instruction that caused the exception.
If an address error occurs during exception processing for a bus error, another
address error, or a reset, the processor halts.
6.2.4 Instruction Traps
Traps are exceptions caused by instructions. They arise from either processor
recognition of abnormal conditions during instruction execution or from use of
specific trapping instructions. Traps are generally used to handle abnormal
conditions that arise in control routines.
The TRAP instruction, which always forces an exception, is useful for
implementing system calls for user programs. The TRAPcc, TRAPV, CHK, and
CHK2 instructions force exceptions when a program detects a run-time error.
The DIVS and DIVU instructions force an exception if a division operation is
attempted with a divisor of zero.
Exception processing for traps folilows the regular sequence.
If tracing is
enabled when an instruction that causes a trap begins execution, a trace
exception will be generated by the instruction, but the trap handler routine will
not be traced (the trap exception will be processed first, then the trace
exception).
CPU32 REFERENCE MANUAL
EXCEPTION PROCESSING
MOTOROLA
6-9
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