Table of Contents
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Figure
Number
LIST OF ILLUSTRATIONS
Title
Page
Number
1-1
Loop Mode Instruction Sequence ........................................................... 1-3
1-2
CPU32 Block Diagram ............................................................................... 1-8
2-1
User Programming Model ......................................................................... 2-2
2-2
Supervisor Programming Model Supplement ..................................... 2-2
2-3
Status Register ............................................................................................ 2-3
2-4
Data Organization in Data Registers ........................................ , .............. 2-5
2-5
Address Organization in Address Registers .......................................... 2-6
2-6
Memory Operand Addressing .................................................................. 2-8
3-1
Single-Effective-Address Instruction Operation Word ......................... 3-1
3-2
Effective Address Specification Formats ................................................ 3-12
3-3
Using SIZE in the Index Selection ........................................................... 3-14
3-4
Using Absolute Address with Indexes .................................................... 3-15
3-5
Addressing Array Items .............................................................................. 3-16
3-6
M68000 Family Address Extension Words ............................................ 3-17
4-1
Instruction Word General Format ........................................................... .4-3
4-2
Instruction Description Format ................................................................ .4-19
4-3
Table Example 1 ......................................................................................... 4-196
4-4
Table Example 2 ......................................................................................... 4-197
4-5
Table Example 3 .....
~
................................................................................... 4-199
6-1
Exception Stack Frame .............................................................................. 6-4
6-2
Reset Operation Flowchart ........................................................................ 6-7
6-3
Format $0 - Four-Word Stack Frame .................................................... 6-27
6-4
Format $2 - Six-Word Stack Frame ...................................................... 6-28
6-5
Internal Transfer Count Register. ............................................................. 6-28
6-6
Format $C - BERR Stack for Prefetches and Operands .................... 6-29
6-7
Format $C - BERR Stack During Four- or Six-Word Stack ............... 6-30
6-8
Format $C = m BERR Stack on MOVEM Operand ............................... 6-30
7-1
In-Circuit Emulator Configuration ........................................................... .7-2
7-2
Bus State Analyzer Configuration ........................................................... 7-2
7-3
BDM Block Diagram ................................................................................... 7-3
7-4
BDM Command Execution Flowchart ..................................................... 7-6
7 -5
Debug Serial I/O Block Diagram ............................................... , .............. 7-9
7-6
Serial Interface Timing Diagram .............................................................. 7-10
7-7
BKPT Timing for Single Bus Cycle .......................................................... 7-11
CPU32 REFERENCE MANUAL
MOTOROLA
xi
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