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II
ADDX
15
14
13
12
11
10
9
8
7
6
I
1
I
o
I
REGISTER
Rx
SIZE
Size Field: 00 = Byte 01 = Word 10= Long
RIM Field: 0
=
Data Register to Data Register 1
=
Memory to Memory
If RIM
=
0, both registers must be data registers
5 4 3
2
0
REGISTERRy
If RIM
=
1, both registers must be address registers for Predecrement Addressing mode
ASL, ASR (Register)
15
14
13
12
11
10
9
8
7
6
I
1 I
1 I
1
I
0
ICOUNTIREGISTERI
dr
SIZE
Count/Register Field:
If I/R Field = 0, Specifies Shift Count
If IIR Field = 1, Specifies Data Register that contains Shift Count
dr Field: 0 = Right 1 = Left
Size Field: 00 = Byte 01 = Word 10 = Long
I/R Field: 0
=
Immediate Shift Count 1
=
Register Shift Count
LSL, LSR (Register)
15
14
13
12
11
10
9
8
7
6
I
1 I
1 I
1
I
0
I COUNTIREGISTERI
dr
SIZE
Count/Register Field:
If I/R Field = 0, Specifies Shift Count
If I/R Field = 1, Specifies Data Register that contains Shift Count
dr Field: 0 = Right 1 = Left
Size Field: 00 = Byte 01 = Word 10 = Long
I/R Field: 0 = Immediate Shift Count 1
=
Register Shift Count
ROXL, ROXR (Register)
15
14
13
12
11
10
9
8
7
6
I
1 I
1 I
1
I
0
ICQUNTIREGISTERI
dr
SIZE
Count/Register Field:
If IIR Field = 0, Specifies Shift Count
If I/R Field = 1, Specifies Data Register that contains Shift Count
dr Field: 0 = Right 1 = Left
Size Field: 00 = Byte 01 = Word 10 = Long
I/R Field: 0 = Immediate Shift Count 1 = Register Shift Count
MOTOROLA
4-192
INSTRUCTION SET
5
4
3
2
1
0
ilr
0
I
0
REGISTER
5
4
3
2
1
0
i/r
0
1
REGISTER
5
4
3
2
0
i/r
1 I
0
I
REGISTER
CPU32 REFERENCE MANUAL
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