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8.3 INSTRUCTION TIMING TABLES
The following assumptions apply to the times shown in the tables in this section:
- A 16-bit data bus is used for all memory accesses.
-
Memory access times are based on two clock bus cycles with no wait
states.
-
The instruction pipeline is full at the beginning of the instruction and is
refilled by the end of the instruction.
Three values are listed for each instruction and addressing mode:
Head
The number of cycles available at the beginning of an instruction
to complete a previous instruction write or to perform a prefetch.
Tail
The number of cycles an instruction uses to complete a write.
Cycles
Four numbers per entry, three contained in parentheses.
The outer number is the minimum number of cycles required for
the instruction to complete.
Numbers within the parentheses represent the number of bus
accesses performed by the instruction.
The first number is the number of operand read accesses
performed by the instruction.
The second number is the number of instruction fetches
performed by the instruction, including all prefetches that keep
the instruction and the instruction pipeline filled.
The third number is the number of write accesses performed by
the instruction.
As an example, consider an AOO.L (12, A3, 07.W
*
4), 02 instruction.
Section 8.3.5 Arithmetic/Logic Instructions shows that the instruction has
~
a head
=
0, a tail
=
0, and cycles
=
2 (0/1/0). However, in indexed, address
~
register Indirect addressing mode, additional time is required to fetch the
effective address.
CPU32 REFERENCE MANUAL
INSTRUCTION EXECUTION
TIMING
MOTOROLA
8-11
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