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8.3.10 Bit Manipulation Instructions
The bit manipulation instruction table indicates the number of clock periods
needed for the processor to perform the specified operation on the given
addressing mode. The total number of clock cycles is outside the parentheses.
The numbers inside parentheses (r/p/w) are included in the total clock cycle
number. All timing data assumes two-clock reads and writes.
MOTOROLA
8-24
Instruction
Head
Tall
Cycles
BCHG
#,On
2
0
6(0/2/0)*
BCHG
On,Om
4
0
6(0/1/0)
BCHG
#, (FEA)
1
2
8(0/2/1 )*
BCHG
On, (FEA)
2
2
8(0/1/1 )
BClR
#,On
2
0
6(0/2/0)*
BClR
On,Om
4
0
6(0/1/0)
BClR
#, (FEA)
1
2
8(0/2/1 )*
BClR
On, (FEA)
2
2
8(0/1/1 )
BSET
#,On
2
0
6(0/2/0)*
BSET
On,Om
4
0
6(0/1/0)
BSET
#, (FEA)
1
2
8(0/2/1 )*
BSET
On, (FEA)
2
2
8(0/1/1 )
BTST
#,On
2
0
4(0/2/0)*
BTST
On,Om
2
0
4(0/1/0)
BTST
#, (FEA)
1
0
4(0/2/0)*
BTST
On, (FEA)
2
0
8(0/1/0)
*An # fetch effective address time must be added for this instruction:
(FEA)
+
(FEA)
+
(OPER)
INSTRUCTION EXECUTION
CPU32 REFERENCE MANUAL
TIMING
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