Motorola CPU32 Reference Manual page 239

M68300 series central processor unit
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III
TRAPV
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
I
1
I
0
I
0
I
1
I
1
I
0
I
0
I
1
I
1
I
1
I
0
I
1
I
1
I
RTR
15
14
13
12
11
10
9
8
7
6
5
4
3
2
0
I
0
I
0
I
1
0
I
0
I
1
0
I
MOVEC
15
14
13
12
10
9
8
7
4
2
dr Field: 0 = Control Register to General Register 1 = General Register to Control Register
Control Register Field:
$000
=
SFC
$801 = VBR
$001 = DFC
$802= CAAR
$002 = CACR
$803= MSP
$800 = USP
$804= ISP
JSR
15
14
13
12
11
10
9
8
7
6
5
4
3
2
EFFECTIVE ADDRESS
0
1
0
0
1
1
1
0
1
0
I
MODE
REGISTER
JMP
15
14
13
12
11
10
9
8
7
6
5
4
3
2
EFFECTIVE ADDRESS
0
1
0
0
1
1
1
0
1
1
I
MODE
REGISTER
ADDQ
15
14
13
12
11
10
9
8
7
6
5
4
3
2
EFFECTIVE ADDRESS
0
1
0
1
DATA
0
SIZE
I
MODE
REGISTER
Data Field: Three bits of immediate data; 000-111 represent values of 1-7; 000 represents 8
Size Field: 00 = Byte 01 = Word 10 = Long
0
0
I
0
1
0
0
o
o
MOTOROLA
4-186
INSTRUCTION SeT
CPU32 REFERENCE MANUAL

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