Motorola CPU32 Reference Manual page 290

sP~
+$02
+$06
15
STATUS REGISTER
PROGRAM COUNTER HIGH
PROGRAM COUNTER LOW
0 1 0
I
0
I
0
I
VECTOR OFFSET
Figure 6-3. Format $0 - Four-Word Stack Frame
6.4.2 Normal Six-Word Stack Frame
o
This stack frame (see Figure 6-4) is created by instruction-related traps, which
include CHK, CHK2, TRAPcc, TRAPV, and divide-by-zero, and by trace
exceptions. The faulted instruction program counter value is the address of the
instruction that caused the exception. The next program counter value (the
address to which RTE returns) is the address of the next instruction to be
executed.
SP~
+$02
+$06
+$08
15
o
STATUS REGISTER
NEXT INSTRUCTION PROGRAM COUNTER HIGH
NEXT INSTRUCTION PROGRAM COUNTER LOW
o
J
0
I
1
J
0
I
VECTOR OFFSET
FAULTED INSTRUCTION PROGRAM COUNTER HIGH
FAULTED INSTRUCTION PROGRAM COUNTER LOW
Figure 6-4. Format $2 - Six-Word Stack Frame
Hardware breakpoints also utilize this format. The faulted instruction program
counter value is the address of the instruction executing when the breakpoint
was sensed. Usually this is the address of the instruction that caused the
breakpoint, but, because released writes can overlap following instructions, the
faulted instruction program counter may point to an instruction following the
instruction that caused the breakpoint. The address to which RTE returns is the
address of the next instruction to be executed
6.4.3 BERR Stack Frame
This stack frame is created when a bus cycle fault is detected. The CPU32
BERR stack frame differs significantly from the equivalent stack frames of other
CPU32 REFERENCE MANUAL EXCEPTION PROCESSING MOTOROLA
6-27