Table of Contents
Advertisement
Ell
8.3.12 Control Instructions
The control instruction table indicates the number of clock periods needed for
the processor to perform the specified operation on the given addressing mode.
Footnotes indicate when to account for the appropriate effective address times.
The total number of clock cycles is outside the parentheses. The numbers
inside parentheses (r/p/w) are included in the total clock cycle number. All
timing data assumes two-clock reads and writes.
MOTOROLA
8-26
Instruction
Head
Tail
Cycles
ANDI
#,SR
0
-2
12(0/2/0)
EaRl
#, SR
0
-2
12(0/2/0)
ORI
#,SR
0
-2
12(0/2/0)
ANDI
#,CCR
2
0
6(0/2/0)
EaRl
#,CCR
2
0
6(0/2/0)
ORI
#,CCR
2
0
6(0/2/0)
BSR.B
3
-2
13(0/2/2)
BSR.W
3
-2
13(0/2/2)
BSR.L
1
-2
13(0/2/2)
CHK
(FEA), Dn (no ex)
2
0
8(0/1/0)
CHK
(FEA), Dn (ex)
2
-2
42(2/2/6)
CHK2 (Save)
(FEA), Dn (no ex)
1
1
3(0/1/0)
CHK2 (Op)
(FEA), Dn (no ex)
2
0
18(XlO/0)
CHK2 (Save)
(FEA), Dn (ex)
1
1
3(0/1/0)
CHK2 (Op)
(FEA), Dn (ex)
2
-2
52(x
+
2/1/6)
JMP
(CEA)
0
-2
6(0/2/0)
JSR
(CEA)
3
-2
13(0/2/2)
LEA
(CEA), An
0
0
2(0/1/0)
LlNK.W
An, #
2
0
10(0/2/2)
LlNK.L
An, #
0
0
10(0/3/2)
Nap
0
0
2(0/1/0)
PEA
(CEA)
0
0
8(0/1/2)
RID
#
1
-2
12(2/2/0)
RlR
1
-2
14(3/2/0)
RTS
1
-2
12(2/2/0)
UNLK
An
1
0
9(2/1/0)
X
=
There is one bus cycle for byte and word operands and two bus cycles for long operands.
For long bus cycles, add two clocks to the tail and to the number of cycles.
NOTE: The CHK2 instruction involves a save step which other instructions do not have. To
calculate total the instruction time, calculate the Save, the effective address, and
the Operation execution times, and combine in the order listed, using the equations
given in 8.1.6 Instruction Execution Time Calculation.
INSTRUCTION EXECUTION
CPU32 REFERENCE MANUAL
TIMING
Advertisement
Table of Contents
