Table of Contents
Advertisement
Ell
Instruction
Head
Tall
Cycles
Notes
On
-
-
0(0/0/0)
-
An
-
-
0(0/0/0)
-
(An)
1
1
3
(X/OIO)
1
(An)+
1
1
3
(X/O/O)
1
-(An)
2
2
4
(X/O/O)
1
(d16.An) or (d16 ,PC)
1
3
5(X/1/0)
1,3
(xxx).W
1
3
5(X/1/0)
1
(xxx).L
1
5
7
(X/2/0)
1
#(data).B
1
1
3(0/1/0)
1
#(data).W
1
1
3(0/1/0)
1
#(data).L
1
3
5(0/2/0)
1
(ds,An,Xn.Sz*Sc) or (ds,PC,Xn.Sz*Sc)
4
2
8(X/1/0)
1,2,3,4
(0) (All Suppressed)
2
2
6(X/1/0)
1,4
(d16)
1
3
7(X/2/0)
1,4
(d32)
1
5
9 (X/3/0)
1,4
(An)
1
1
5(X/1/0)
1,2,4
(Xm.Sz*Sc)
4
2
8(X/1/0)
1,2,4
(An,Xm.Sz*Sc)
4
2
8(X/1/0)
1,2,3,4
(d16 ,An) or (d16 ,PC)
1
3
7
(XI2IO)
1,3,4
(d32,An) or (d32 ,PC)
1
5
9 (X/3/0)
1,3,4
(d16,An,Xm) or (d16,PC,Xm)
2
2
8
(X/2/0)
1,3,4
(d32.An,Xm) or (d32,PC,Xm)
1
3
9 (X/3/0)
1,3,4
(d16,An,Xm.Sz*Sc) or (d16,PC,Xm.Sz*Sc)
2
2
8
(x/2/0)
1,2,3,4
(d32,An,Xm.Sz*Sc) or (d32,PC,Xm.Sz*Sc)
1
3
9 (X/3/0)
1,2,3,4
X
=
There is one bus cycle for by1e and word operands and two bus cycles for long operands.
For long bus cycles, add two clocks to the tail and to the number of cycles.
NOTES:
1. The read of the effective address and replacement fetches overlap the head of the
operation by the amount specified in the tail.
2.
Size and scale of the index register do not affect execution time.
3. The program counter may be substituted for the base address register An.
4. When adjusting the prefetch time for slower buses, extra clocks may be subtracted from
the head until the head reaches zero, at which time additional clocks must be added to
both the tail and cycle counts.
MOTOROLA
8-14
INSTRUCTION EXECUTION
CPU32 REFERENCE MANUAL
TIMING
Advertisement
Table of Contents
