Motorola CPU32 Reference Manual page 295

7.1.2
A resident debugger simplifies implementation of an in-circuit emulator. In a
common setup (see Figure 7-1), emulator hardware replaces the target system
processor. A complex, expensive pod-and-cable interface provides a
communication path between target system and emulator.
By contrast, an integrated debugger supports use of a bus state analyzer (BSA)
for in-circuit emulation. The processor remains in the target system (see Figure
7-2) and the interface is simplified. The BSA monitors target processor
operation and the on-chip debugger controls the operating environment.
Emulation is much "closer" to target hardware, and many interfacing problems
(i.e., limitations on high-frequency operation, AC and DC parametric
mismatches, and restrictions on cable length) are minimized.
IN-CIRCUIT
EMULATOR
TARGET
l,
SYSTEM
A
"I
TARGET
1;-
"'I
1' 1
PROCESSOR
I"'
,.
Figure 7-1. In-Circuit Emulator Configuration
TARGET
SYSTEM
I
TARGET
I,
BUS STATE
, ; '
...
l,
PROCESSOR
I
,.
ANALYZER ...
...
Figure 7-2. Bus State Analyzer Configuration
Deterministic Opcode Tracking Overview
CPU32 function code outputs are augmented by two supplementary signals that
monitor the instruction pipeline. The instruction fetch (IFETCH) output identifies
bus cycles in which data is loaded into the pipeline, and signals pipeline
flushes. The instruction pipe (IPIPE) output indicates when each mid-
instruction pipeline advance occurs and when instruction execution begins.
These signals allow a BSA to synchronize with instruction stream activity. Refer
to 7.3 Deterministic Opcode Tracking for complete information.
MOTOROLA
7-2
DEVELOPMENT SUPPORT CPU32 REFERENCE MANUAL