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One clock period after the synchronized DSCLK has been seen internally, the
updated counter value is checked. If the counter has reached zero, the receive
data latch is updated from the input shift register. At this same time, the output
shift register is reloaded with the "not ready/come again" response. Once the
receive data latch has been loaded, the CPU is released to act on the new data.
Response data overwrites the "not ready" response when the CPU has
completed the current operation.
Data written into the output shift register appears immediately on the DSO
signal. In general, this action changes the state of the signal from a high ("not
ready" response status bit) to a low (valid data status bit) logic level. However,
this level change only occurs if the command completes successfully. Error
conditions overwrite the "not ready" response with the appropriate response
that also has the status bit set.
A user can use the state change on DSO to signal hardware that the next serial
transfer may begin. A timeout of sufficient length to trap error conditions that do
not change the state of DSO should also be incorporated into the design.
Hardware interlocks in the CPU prevent result data from corrupting serial
transfers in progress.
7.2.7.2 Development System Serial Logic
The development system, as the master of the serial data link, must supply the
serial clock. However, normal and BDM operations could interact if the clock
generator is not properly designed.
Breakpoint requests are made by asserting BKPT to the low state in either of
two ways. The primary method is to assert BKPT during a single bus cycle for
which an exception is desired.
Another method is to assert B K P T, then
continue to assert it until the CPU32 responds by asserting FREEZE. This
method is useful for forcing a transition into BDM when the bus is not being
monitored.
Each of these methods requires a slightly different serial logic
design to avoid spurious serial clocks.
MOTOROLA
7·12
DEVELOPMENT
SUPPORT
CPU32 REFERENCE MANUAL
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