Motorola CPU32 Reference Manual page 260

5.2.3 Changing Privilege Level
To change from user privilege level to supervisor privilege level, a condition that
causes exception processing must occur. When exception processing begins,
the current values in the status register, including the S bit, are saved on the
supervisor stack, and then the S bit is set, enabling supervisory access.
Execution continues at supervisor level until exception processing is complete.
To return to user access level, a system routine must execute one of the
following instructions: MOVE to SR, ANDI to SR, EORI to SR, ORI to SR, or RTE.
These instructions execute only at supervisor privilege level, and can modify the
S bit of the status register. After these instructions execute, the instruction
pipeline is flushed, then refilled from the appropriate address space.
The RTE instruction causes a return to a program that was executing when an
exception occurred. When RTE is executed, the exception stack frame saved
on the supervisor stack can be restored in either of two ways.
If the frame was generated by an interrupt, breakpoint, trap, or instruction
exception, the status register and program counter are restored to the values
saved on the supervisor stack, and execution resumes at the restored program
counter address, with access level determined by the S bit of the restored status
register.
If the frame was generated by a bus error or an address error exception, the
entire processor state is restored from the stack.
5.3 Types of Address Space
During each bus cycle, the processor generates function code signals that
permit selection of eight distinct 4-gigabit address spaces. Not all devices that
incorporate the CPU32 support a full complement of memory. (Refer to the
appropriate user's manual for details.) Selection varies according to the access
required. Automatic selection of supervisor and user space, and of program
and data space, is provided. In addition, certain special processor cycles, such
as the interrupt acknowledge cycle or the LPSTOP broadcast, cycle are
recognized, and appropriate codes are generated. Table 5-1 shows function
code values and the corresponding address space.
CPU32 REFERENCE MANUAL PROCESSING STATES
MOTOROLA
5-3
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