Motorola CPU32 Reference Manual page 340

General observations regarding calculation of execution time are as follows:
Any time the number of bus cycles is listed as "X", substitute a value of one for
byte and word cycles and a value of two for long cycles. For long bus cycles,
usually add a value of two to the tail.
The time calculated for an instruction on a three-clock (or longer) bus is
usually longer than the actual execution time. All times shown are for two-
clock bus cycles.
If the previous instruction has a negative tail, then a prefetch for the current
instruction can begin during the execution of that previous instruction.
Certain instructions requiring an immediate extension word (immediate word
effective address, absolute word effective address, address register indirect
with displacement effective address, conditional branches with word offsets,
bit operations, LPSTOP, TBL, MOVEM, MOVEC, MOVES, MOVEP, MUL.L,
OIV.L, CHK2, CMP2, and OBcc) are not permitted to begin until the extension
word has been in the instruction pipeline for at least one cycle. This does not
apply to long offsets or displacements.
8.3.1 Fetch Effective Address
The fetch effective address table indicates the number of clock periods needed
for the processor to calculate and fetch the specified effective address. The total
number of clock cycles is outside the parentheses. The numbers inside
parentheses (r/p/w) are included in the total clock cycle number. All timing data
assumes two-clock reads and writes.
CPU32 REFERENCE MANUAL . INSTRUCTION EXECUTION
TIMING
MOTOROLA
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