Motorola CPU32 Reference Manual page 329

II
ADDRESS
BUS
EXECUTION UNIT
PROGRAM
COUNTER
SECTION
BUS CONTROL
SIGNALS
DATA
SECTION
DATA
BUS
Figure 8-1. Block Diagram of Independent Resources
8.1.2 Instruction Pipeline
The CPU32 contains a two-word instruction pipeline where instruction opcodes
are decoded. Each stage of the pipeline is initially filled under microsequencer
control and subsequently refilled by the prefetch controller as it empties.
Stage A of the instruction pipeline is a buffer. Prefetches completed on the bus
before stage B empties are temporarily stored in this buffer. Instruction words
(instruction operation words and all extension words) are decoded at stage B.
Residual decoding and execution take place in stage C.
Each pipeline stage has an associated status bit that shows whether the word in
that stage was loaded with data from a bus cycle that terminated abnormally.
MOTOROLA
8-2
INSTRUCTION EXECUTION CPU32 REFERENCE MANUAL
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