Motorola CPU32 Reference Manual page 298

7.2.2.1 External BKPT Signal
Once enabled, 80M is initiated whenever assertion of BKPT is acknowledged.
If 80M is disabled, a breakpoint exception (vector $OC) is acknowledged. The
BKPT input has the same timing relationship to the data strobe trailing edge as
does read cycle data. There is no breakpoint acknowledge bus cycle when
80M is entered.
7.2.2.2 BGND Instruction
An illegal instruction, $4AFA, is reserved for use by development tools. The
CPU32 defines $4AFA (8GNO) to be a 80M entry point when BDM is enabled.
If 80M is disabled, an illegal instruction trap is acknowledged. Illegal
instruction traps are discussed in 6.2.8 Illegal or Unimplemented
Instructions.
7.2.2.3 Double Bus Fault
The CPU32 normally treats a double bus fault, or two bus faults in succession,
as a catastrophic system error, and halts. When this condition occurs during
initial system debug (a fault in the reset logic), further debugging is impossible
until the problem is corrected. In 8DM, the fault can be temporarily bypassed,
so that its origin can be isolated and eliminated.
7.2.2.4 Peripheral Breakpoints
CPU32 peripheral breakpoints are implemented in the same
wa~xternal
breakpoints - peripherals request breakpoints by asserting the BKPT Signal.
Consult the appropriate peripheral user's manual for additional details on the
generation of peripheral breakpoints.
7.2.3 Entering BDM
When the processor detects a breakpoint or a double bus fault, or decodes a
8GNO instruction, it suspends instruction execution and asserts the FREEZE
.w
output. This is the first indication that the processor has entered 80M. Once _ _
FREEZE has been asserted, the CPU enables the serial communication
hardware and awaits a command.
The CPU writes a unique value indicating the source of 80M transition into
temporary register A (ATEMP) as part of the process of entering 80M. A user
can poll ATEMP and determine the source (see Table 7-2) by issuing a read
system register command (RSREG). ATEMP is used in most debugger
commands for temporary storage - it is imperative that the RSREG command
be the first command issued after transition into 80M.
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