Motorola CPU32 Reference Manual page 129

III
DIVU
DIVUL
Instruction Format (long form):
15 14 13 12 11 10
0 1 0 0
1
1
0 REGISTER Dq 1 SIZE
Instruction Fields:
Unslg ned Divide
9
s
7
0
0 0
0 0 0
6 5
1
0 0
I
4
3
DIVU
DIVUL
2
o
EFFECTIVE ADDRESS
MODE REGISTER
o
I
0 REGISTER Dr
Effective Address field - Specifies the source operand. Only data addressing modes are
allowed as shown:
Addressing Mode Mode Register Addressing Mode Mode Register
On 000 Reg. number: On (xxx).w 111 000
An
- -
(xxx).L
111 001
(An) 010 Reg. number: An
#(data)
111 100
(An)
+
011
Reg. number: An
-(An) 100 Reg. number: An
(d16, An)
101
Reg. number: An (d16, PC)
111 010
(dS, An, Xn)
110
Reg. number: An
(de, PC, Xn)
111 011
(bd, An, Xn)
110
Reg. number: An (bd, PC, Xn)
111 011
Register Dq field - Specifies a data register for the destination operand. The low-order 32 bits of
the dividend come from this register, and the 32-bit quotient is loaded into this register.
Size field - Selects a 32 or 64 bit division operation.
o -
32-bit dividend is in Register Dq.
1 - 64-bit dividend is in Dr:Dq.
Register Dr field - After the division, this register contains the 32-bit remainder. If Dr and Dq are
the same register, only the quotient is returned. If Size is 1, this field also specifies the data
register that contains the high-order 32 bits of the dividend.
MOTOROLA
4-76
NOTE
Overflow occurs if the quotient is larger than a 32-bit signed integer.
INSTRUCTION SET
CPU32 REFERENCE MANUAL