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CLKOUT
IPIPE
L-.-l
EXTENSION
WORD USED
\1.-____
- - - 1
INSTRUCTION
EXTENSION
START
WORD USED
INSTRUCTION
START
Figure 7-12. Instruction Pipeline Timing Diagram
IPIPE
should
~sampled
on
the
falling
edge
of
the
clock.
The assertion of IPIPE for a single cycle after one or more cycles of negation
indicates use of the data in IRS (advance of IRA into IRS). Assertion for two
clock cycles indicates that a new instruction has started (both IRA
~
IRS and
IRS
~
IRC transfers have occurred). Loading IRC always indicates that an
instruction is beginning execution -
the opcode is loaded into IRC by the
transfer.
In some cases, instructions using immediate addressing begin executing and
initiate a second pipeline advance at the same time. IPIPE will not be negated
between the two indications, which implies the need for a state machine to track
the state of IPIPE. The state machine can be resynchronized during periods of
inactivity on the signal.
7.3.3 Opcode Tracking during Loop Mode
IPIPE and IFETCH continue to work normally during loop mode.
IFETCH
indicates all instruction fetches up
thro~he
point that data begins
reCirculating within the instruction pipeline. IPIPE continues to signal the start
of instructions and the use of extension words even though data is being
recirculated internally. IFETCH returns to normal operation with the first fetch
after exiting loop mode.
MOTOROLA
7-34
DEVELOPMENT
SUPPORT
CPU32 REFERENCE MANUAL
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