Motorola CPU32 Reference Manual page 332

The execution time attributed to instructions A, B, and C after considering the
overlap is illustrated in Figure 8:.3. The overlap time is attributed to the
execution time of the completing instruction. The following equation shows the
method for calculating the overlap time:
I----INSTRUCTION A - - - - \
I----INSTRUCTION B - - - - \
I----INSTRUCTION C
- - - - - - - i
OVERLAP
PERIOD
(ABSORBED BY
INSTRUCTION A)
OVERLAP
PERIOD
(ABSORBED BY
INSTRUCTION B)
Figure 8-3. Attributed Instruction Times
8.1.5 Effects of Wait States
The CPU32 access time for on-chip memory and peripherals is two clocks.
While· two-clock external accesses are possible when the bus is operated in a
synchronous mode, a typical external memory speed is three or more clocks.
All instruction times listed in this section are for word access only (unless an
explicit exception is given), and are based on the assumption that both
instruction fetches and operand cycles are to a two-clock memory. Any time a
long access is made, time for the additional bus cycle(s) must be added to the
overall execution time. Wait states du'e to slow external memory must be added
to the access time for each bus cycle.
A typical application has a mixture of bus speeds - program execution from an
off-chip ROM, accesses to on-chip peripherals, storage of variables in slow off-
chip RAM, and accesses to external peripherals with speeds ranging from
moderate to very slow. To arrive at an accurate instruction time calculation,
~
each bus access must be individually considered. Many instructions have a
~
head cycle count, which can overlap the cycles of an operand fetch to slower
memory started by a previous instruction. In these cases, an increase in access
time has no effect on the total execution time of the pair of instructions.
CPU32 REFERENCE MANUAL INSTRUCTION EXECUTION
TIMING
MOTOROLA
8-5