Motorola CPU32 Reference Manual page 278

Interrupt recognition and subsequent processing are based on internal interrupt
request signals (IRQ7-IRQ1) and the current priority set in status register priority
mask 1[2:0]. Interrupt request level zero (IRQ7-IRQ1 negated) indicates that no
service is requested. When an interrupt of level one through six is requested
via IRQ6-IRQ1, the processor compares the request level with the interrupt
mask to determine whether the interrupt should be processed. Interrupt
requests are inhibited for all priority levels less than or equal to the current
priority. Level seven interrupts are nonmaskable.
IRQ7-IRQ1 are synchronized and debounced by input circuitry on consecutive
rising edges of the processor clock. To be valid, an interrupt request must be
held constant for at least two consecutive clock periods.
Interrupt requests do not force immediate exception proceSSing, but are left
pending. A pending interrupt is detected between instructions or at the end of
exception processing - all interrupt requests must be held asserted until they
are acknowledged by the CPU. If the priority of the interrupt is greater than the
current priority level, exception processing begins.
Exception processing occurs as follows. First, the processor makes an internal
copy of the status register. After the copy is made, the processor state bits in the
status register are changed - the S bit is set, establishing supervisor access
level, and bits T1 and TO are cleared, disabling tracing. Then, priority level is
set to the level of the interrupt and the processor fetches a vector number from
the interrupting device (CPU space $F). The fetch bus cycle is classified as an
interrupt acknowledge and the encoded level number of the interrupt is placed
on the address bus.
If an interrupting device requests automatic vectoring, the processor generates
a vector number (25 to 31) determined by the interrupt level number.
If the response to the interrupt acknowledge bus cycle is a bus error, the
interrupt is taken to be spurious, and the spurious interrupt vector number (24)
is generated.
The exception vector number, program counter, and status register are saved
on the supervisor stack. The saved value of the program counter is the address
of the instruction that would have executed if the interrupt had not occurred.
Priority level seven interrupt is a special case. Level seven interrupts are
nonmaskable interrupts (NMI). Level seven requests are transition sensitive to
eliminate redundant servicing and concomitant stack overflow. Transition
CPU32 REFERENCE MANUAL EXCEPTION PROCESSING
MOTOROLA
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