Motorola CPU32 Reference Manual page 282

Instruction prefetch faults are distinguished from operand (both read and write)
faults by the IN bit. If IN is cleared, the error was on an operand cycle; if IN is
set, the error was on an instruction prefetch. IN is ignored during unstacking.
o
-Operand
1 - Prefetch
Read and write bus cycles are distinguished by the RW bit. Read bus cycles will
set the bit, and write bus cycles will clear it. The bit is reloaded into the bus
controller if the RR bit is set during unstacking.
0 - Faulted cycle was an operand write
1 - Faulted cycle was a prefetch or operand read
The LG bit indicates an original operand size of long word. LG is cleared if the
original operand was a byte or word - SIZ will indicate original (and
remaining) size. LG is set if the original was a long word - SIZ will indicate the
remaining size at the time of fault. LG is ignored during unstacking.
o -
Original operand size was byte or word
1 - Original operand size was long word
The SSW SIZ field shows operand size remaining when a fault was detected.
This field does not indicate the initial size of the operand. It also does not
necessarily indicate the proper status of a dynamically sized bus cycle.
Dynamic sizing occurs on the external bus and is transparent to the CPU. Byte
size is shown only when the original operand was a byte. The field is reloaded
into the bus controller if the RR bit is set during unstacking. The SIZ field is
encoded as follows:
III
00 - Long word
01 - Byte
10 - Word
11 - Unused, reserved
The function code for the faulted cycle is stacked in the FUNC field of the SSW,
which is a copy of [FC2:FCO] for the faulted bus cycle. This field is reloaded into
the bus controller if the RR bit is set during unstacking. All unused bits are
stacked as zeros and are ignored during unstacking. Further discussion of the
SSW is included in 6.3.1 Types of Faults.
6.3.1 Types of Faults
An efficient implementation of instruction restart dictates that faults on some bus
cycles be treated differently than faults on other bus cycles. The CPU32 defines
CPU32 REFERENCE MANUAL EXCEPTION PROCESSING MOTOROLA
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