Motorola CPU32 Reference Manual page 301

7.2.5.3 Current Instruction Program Counter (PCC)
The PCC holds a pointer to the first word of the last instruction executed prior to
transition into background mode. Due to instruction pipelining, the instruction
pointed to may not be the instruction which caused the transition. An example
is a breakpoint on a released write. The bus cycle may overlap as many as two
subsequent instructions before stalling the instruction sequencer. A breakpoint
asserted during this cycle will not be acknowledged until the end of the
instruction executing at completion of the bus cycle. PCC will contain
$00000001 if BOM is entered via a double bus fault immediately out of reset.
7.2.6 Returning from 80M
BOM is terminated when a resume execution (GO) or call user code (CALL)
command is received. Both GO and CALL flush the instruction pipeline and
refetch instructions from the location pointed to by the RPC.
The return PC and the memory space referred to by the status register SUPV bit
reflect any changes made during BOM. FREEZE is negated prior to initiating
the first prefetch. Upon negation of FREEZE, the serial subsystem is disabled,
and the signals revert to IPIPE/IFETCH functionality.
7.2.7 Serial Interface
Communication with the CPU32 during BOM occurs via a dedicated serial
interface, which shares pins with other development features. The BKPT signal
becomes the serial clock (DSCLK); serial input data (DSI) is received on
IFETCH, and serial output data (OSO) is transmitted on IPIPE.
The serial interface uses a full-duplex synchronous protocol similar to the serial
peripheral interface (SPI) protocol. The development system serves as the
master of the serial link since it is responsible for the generation of OSCLK. If
DSCLK is derived from the CPU32 system clock, development system serial
logic is unhindered by the operating frequency of the target processor.
Operable frequency range of the serial clock is from DC to one-half the
processor system clock frequency.
The serial interface operates in full-duplex mode - data is transmitted and
received simultaneously by both master and slave devices. In general, data
transitions occur on the falling edge of OSCLK and are stable by the following
rising edge of DSCLK. Data is transmitted MSB first, and is latched on the
rising edge of OSCLK.
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