Motorola CPU32 Reference Manual page 299

Table 7-2. Polling the BDM Entry Source
Source
ATEMP
[31 :16]
ATEMP
[15:0]
Double Bus Fault
SSW*
$FFFF
BGND Instruction $0000
$0001
Hardware Breakpoint $0000 $0000
*Special status word (SSW) is described in detail in Section 6.3.Fault
Recovery.
A double bus fault during initial stack pointer/program counter (SP/PC) fetch
sequence is distinguished by a value of $FFFFFFFF in the current instruction
PC. At no other time will the processor write an odd value into this register.
7.2.4 Command Execution
Figure 7-4 summarizes 8DM command execution. Commands consist of one
16-bit operation word and can include one or more 16-bit extension words.
Each incoming word is read as it is assembled by the serial interface. The
microcode routine corresponding to a command is executed as soon as the
command is complete. Result operands are loaded into the output shift register
to be shifted out as the next command is read. This process is repeated for
each command until the CPU returns to normal operating mode.
7.2.5 Background Mode Registers
8DM processing uses three special purpose registers to keep track of program
context during development. A description of each follows.
7.2.5.1 Fault Address Register (FAR)
The FAR contains the address of the faulting bus cycle immediately following a
bus or address error. This address remains available until overwritten by a
subsequent bus cycle. Following a double bus fault, the FAR contains the
address of the last bus cycle. The address of the first fault (if there was one) is
not visible to the user.
7.2.5.2 Return Program Counter (RPC)
The RPC points to the location where fetching will commence after transition
from background mode to normal mode. This register should be accessed to
change the flow of a program under development. Changing the RPC to an odd
value will cause an address error when normal mode prefetching begins.
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DEVELOPMENT SUPPORT CPU32 REFERENCE MANUAL