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COMMANDS TRANSMITIED TO THE CPU
COMMAND CODE TRANSMIITED DURING THIS CYCLE
HIGH-ORDER 16 BITS OF MEMORY ADDRESS
LOW-ORDER 16 BITS OF MEMORY ADDRESS
SEQUENCE TAKEN IF
ILLEGAL COMMAND
IS RECEIVED BY CPU
DATA UNUSED FROM
THIS TRANSFER
RESULTS FROM PREVIOUS COMMAND
RESPONSES FROM THE CPU
NONSERIAL-RELATED ACTIVITY
SEQUENCE TAKEN IF BUS ERROR
OR ADDRESS ERROR OCCURS ON
MEMORY ACCESS
HIGH AND LOW-ORDER
16 BITS OF RESULT
Figure 7-10. Command-Sequence-Diagram Example
7.2.8.3 Command Set Summary
The 8DM command set is summarized in Table 7-4. Subsequent paragraphs
contain detailed descriptions of each command.
CPU32 REFERENCE MANUAL
DEVELOPMENT SUPPORT
MOTOROLA
7-17
III
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