Motorola CPU32 Reference Manual page 38

For brief format addressing, the address of the operand is the sum of the
address in the address register, the sign-extended displacement integer in the
low-order eight bits of the extension word, and the index operand. The
reference is classed as a data reference, except for the JMP and JSR
instructions. The index operand is specified" Ri.sz*scl".
GENERATION:
ASSEMBLER SYNTAX:
MODE:
REGISTER:
ADDRESS REGISTER:
DISPLACEMENT:
INDEX REGISTER:
SCALE:
MEMORY ADDRESS:
31
EA = (An) + (Xn*SCALE) + dB
(dB. An. SIZE*SCALE)
110
n
31
An----~
MEMORY ADDRESS
~------------------~--~
~
=
=SI~ EEE~E~
=
- - L _ _ _ _ _ _
-----lt------~
31
SIGN-EXTENDED VALUE
SCALE VALUE
31
NUMBER OF EXTENSION WORDS:
OPERAND
"Ri" specifies a general data or address register used as an index register. The
index operand is derived from the index register. The index register is a data
register if bit [15]
=
0 in the first extension word and an address register if bit [15]
=
1. The index register number is given by extension word bits [14:12].
Index size is referred to as "sz". It may be either "W" or "L". Index size is given
by bit [11] of the extension word. If bit [11]
=
0, the index value is the sign-
extended low-order word integer of the index register (W). If bit [11]
=
1, the
index value is the long integer in the index register (L).
The term "sci" refers to index scale selection and may be 1, 2, 4, or 8. The
index value is scaled according to bits [10:9]. Codes 00, 01, 10, or 11 select
index scaling of 1, 2, 4, or 8, respectively.
CPU32 REFERENCE MANUAL DATA ORGANIZATION AND
ADDRESSING CAPABILITIES
MOTOROLA
3-7
IIJ