Motorola CPU32 Reference Manual page 266

6.1.2 Types of Exceptions
An exception can be caused by internal or external events.
An internal exception can be generated by an instruction or by an error. The
TRAP, TRAPcc, TRAPV, BKPT, CHK, CHK2, RTE, and DIV instructions can
cause exceptions during normal execution. Illegal instructions, instruction
fetches from odd addresses, word or long-word operand accesses from odd
addresses, and privilege violations also cause internal exceptions.
Sources of external exception include interrupts, breakpoints, bus errors, and
reset requests. Interrupts are peripheral device requests for processor action.
Breakpoints are used to support development equipment. Bus error and reset
are used for access control and processor restart.
6.1.3 Exception Processing Sequence
For all exceptions other than a reset exception, exception processing occurs in
the following sequence. Refer to
6.2.1
Reset for details of reset processing.
As exception processing begins, the processor makes an internal copy of the
status register. After the copy is made, the processor state bits in the status
register are changed - the S bit is set, establishing supervisor access level,
and bits T1 and TO are cleared, disabling tracing. For reset and interrupt
exceptions, the interrupt priority mask is also updated.
Next, the exception number is obtained. For interrupts, the number is fetched
from CPU space $F(the bus cycle is an interrupt acknowledge). For all other
exceptions, internal logic provides a vector number.
Next, current processor status is saved. An exception stack frame is created
lID
and placed on the supervisor stack. All stack frames contain copies of the
status register and the program counter for use by RTE. The type of
exception and the context in which the exception occurs determine what
other information is stored in the stack frame.
Finally, the processor prepares to resume normal execution of instructions.
The exception vector offset is determined by multiplying the vector number by
four, and the offset is added to the contents of the VBR to determine
displacement into the exception vector table. The exception vector is loaded
into the program counter. If no other exception is pending, the processor will
resume normal execution at the new address in the PC.
CPU32 REFERENCE MANUAL
EXCEPTION PROCESSING MOTOROLA
6-3