Motorola CPU32 Reference Manual page 274

Exception processing follows the regular sequence. Vector number 12 (offset
$30) is internally generated. The program counter of the currently executing
instruction, the program counter of the next instruction to execute, and a copy of
the status register are saved on the supervisor stack.
6.2.7 Format Error
The processor checks certain data values for control operations. The validity of
the stack format code and, in the case of a bus cycle fault format, the version
number of the processor that generated the frame are checked during execution
of the RTE instruction. This check ensures that the program does not make
erroneous assumptions about information in the stack frame.
If the format of the control data is improper, the processor generates a format
error exception. This exception saves a four-word format exception frame and
then vectors through vector table entry number 14. The stacked program
counter is the address of the RTE instruction that discovered the format error.
6.2.8 Illegal or Unimplemented Instructions
An instruction is illegal if it contains a word bit pattern that does not correspond
to the bit pattern of the first word of a legal CPU32 instruction, if it is a MOVEC
instruction that contains an undefined register specification field in the first
extension word, or if it contains an indexed addressing mode extension word
with bits [5:4]
=
00 or bits [3:0]
*
0000.
If an illegal instruction is fetched during instruction execution, an illegal
instruction exception occurs. This facility allows the operating system to detect
program errors or to emulate instructions in software.
Word patterns with bits [15:12]
=
1010 (referred to as A-line opcodes) are
unimplemented instructions. A separate exception vector (vector 10, offset $28)
is given to unimplemented instructions to permit efficient emulation.
Word patterns with bits [15:12]
=
1111 (referred to as F-line opcodes) are used
for M68000 Family instruction set extensions. They can generate an
unimplemented instruction exception caused by the first extension word of the
instruction or by the addressing mode extension word. A separate F-line
emulation vector (vector 11 , offset $2C) is used for the exception vector.
All unimplemented instructions are reserved for use by Motorola for
enhancements and extensions to the basic M68000 architecture. Opcode
pattern $4AFC is defined to be illegal on all M68000 Family members. Those
customers requiring the use of an unimplemented opcode for synthesis of
"custom instructions," operating system calls, etc., should use this opcode.
CPU32 REFERENCE MANUAL EXCEPTION PROCESSING MOTOROLA
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