Motorola CPU32 Reference Manual page 296

7.1.3 On-Chip Hardware Breakpoint Overview
An external breakpoint input and an on-chip hardware breakpoint capability
permit breakpoint trap on any memory access. Off-chip address comparators
preclude breakpoints on internal accesses unless show cycles are enabled.
Breakpoints on prefetched instructions, which are flushed from the pipeline
before execution, are not acknowledged, but operand breakpoints are always
acknowledged. Acknowledged breakpoints can initiate either exception
processing or background debug mode (BOM). See 6.2.6 Hardware
Breakpoints for more information.
7.2 Background Debug Mode (BOM)
BOM is an alternate CPU32 operating mode. Ouring BOM, normal instruction
execution is suspended, and special microcode performs debugging functions
under external control. Figure 7-3 is a BOM block diagram.
MICROCODE
EXECUTION
UNIT
CPU32 REFERENCE MANUAL
SERIAL
INTERFACE
t-------+--'--+-i~ IPIPE/DSO
SEQUENCER
1--_ _ _
----1. _
_+_;~
IFETCHIDSI
BUS
CONTROL
Figure 7-3. BDM Block Diagram
DEVELOPMENT SUPPORT
BKPTIDSCLK
DATA BUS
BERR
FREEZE
ADDRESS BUS
MOTOROLA
7-3