Motorola CPU32 Reference Manual page 331

II
8.1.3.3 Microbus Controller
The microbus controller performs bus cycles issued by the microsequencer.
Operand accesses always have priority over instruction prefetches. Word and
byte operands are accessed in a single CPU-initiated bus cycle, although the
external bus interface may be required to initiate a second cycle when a word
operand is sent to a byte-sized external port. Long operands are accessed in
two bus cycles, most significant word first.
The instruction pipeline is capable of recognizing instructions that cause a
change of flow. It informs the bus controller when a change of flow is imminent,
and the bu,s controller refrains from starting prefetches that would be discarded
due to the change of flow.
8.1.4 Instruction Execution Overlap
Overlap is the time, measured in clock cycles, that an instruction executes
concurrently with the previous instruction. As shown in Figure 8-2, portions of
instructions A and B execute simultaneously, so that total execution time is
reduced. Because portions of instructions Band C also overlap, overall
execution time for all three instructions is also reduced.
Each instruction contributes to the total overlap time. The portion of execution
time at the end of instruction A that can overlap the beginning of instruction B is
called the tail of instruction A. The portion of execution time at the beginning of
instruction B that can overlap the end of instruction A is called the head of
instruction B. The total overlap time between instructions A and B is the smaller
tail of A and the head of B.
I------INSTRUCTION A - - - - - i
MOTOROLA
8-4
I-----INSTRUCTION B
- - - - - - - l
t-----INSTRUCTION C - - - - - i
OVERLAP
OVERLAP
Figure 8-2. Simultaneous Instruction Execution
INSTRUCTION EXECUTION CPU32 REFERENCE MANUAL
TIMING